As operating frequencies and circuit densities have increased, energy dissipation and power flux have become problematic in a wide variety of digital devices, ranging from small portable systems, (e.g. laptops and Personal Digital Assistants), where battery size, weight and operational life are critical, to large computing machines where cooling and power supply pose substantial packaging problems. Power consumption and dissipation within digital electronic devices is largely attributable to switching activities occurring within components of such devices. In conventional Complementary Metal-oxide Semiconductor (CMOS) switches, dissipation is primarily attributable to the transfer of charge from a voltage source to a gate capacitance through a switching device which is resistive. By way of explanation, reference is made FIG. 1, which shows a simple CMOS inverter circuit 10. A logic input 12 is provided to the gate terminals on a P-channel MOS (pMOS) switch 14 and N-channel MOS (nMOS) switch 16, the drain terminals of the pMOS and nMOS switches being coupled to the node 18. A capacitor 20 is coupled between the node 18 and ground. As will be appreciated, when the input 12 is driven low, the pMOS 14 switches on, thus causing the capacitor 20 to be charged from the voltage source V.sub.CC through the pMOS switch 14, and a logical one (HIGH) is registered at node 18. Similarly, when the input 12 is driven high, the pMOS switch 14 switches off, and the nMOS switch 16 switches on, thus allowing charge stored in the capacitor 20 to be transferred via the nMOS switch 16 to ground, whereafter a logical zero (0) is registered at node 18. Each transition of the input signal 12 results in the transfer of a certain amount of charge across one of the switches 14 or 16. In conventional CMOS switches, such as those shown in FIG. 1, each transfer of charge is coupled with the dissipation of a certain amount of energy, which is approximately 1/2 CV.sub.CC 2. A number of methods of reducing this quantity of energy dissipation have been proposed, including reducing the operating voltage V.sub.CC, reducing the capacitance C, and reducing the number of switching operations which occur within an integrated circuit.
Recently, the concept of adiabatic circuits has been proposed as a method of reducing energy dissipation. Simply stated, adiabatic computing seeks to avoid the occurrence of a sudden and large potential difference across a switch when that switch is closed, and in this way to limit power dissipation. As the power dissipated across a resistive device, such as a switch, is equal to I.sup.2 R, by controlling the rate at which charge traverses the switch (i.e. the current), it is possible to limit the energy dissipated. Accordingly, adiabatic circuits strive to:
(1) only close a switch when the potential difference across the switch is zero (or at least at a minimum); and PA0 (2) slowly increase, or ramp, a voltage source from which charge is transferred across the switch. It will be appreciated that the slower the rate of increase of the voltage, the slower the rate at which the charge will traverse the switch, and the less the energy dissipated.
The challenge facing the designers of adiabatic circuit is the implementation of large logic blocks using gates which maximize the number of times switches are closed with zero, or minimal, potential differences across the switches. A number of circuits and methodologies of implementing adiabatic circuits have been disclosed in the prior art. However, these circuits have included large numbers of switching devices, as well as large numbers of power clock inputs.